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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004, zarlink semiconductor inc. all rights reserved. features ? 1024 channel x 1024 channel non-blocking digital time division multiplex (tdm) switch at 4.096, 8.192 or 16.384 mbps ? 16 serial tdm input, 16 serial tdm output streams ? output streams can be configured as bi- directional for connection to backplanes ? exceptional input clock cy cle to cycle variation tolerance (20 ns for all rates) ? per-stream input bit delay with flexible sampling point selection ? per-stream output bit and fractional bit advancement ? per-channel constant or variable throughput delay for frame integrity and low latency applications ? per-channel high impedance output control ? per-channel message mode ? input clock: 4.096 mhz, 8.192 mhz, 16.384 mhz ? input frame pulses:61 ns, 122 ns, 244 ns ? control interface compatible with intel and motorola 16-bit non-multiplexed buses ? connection memory block programming ? supports st-bus and gci-bus standards for input and output timing ? ieee-1149.1 (jtag) test port ? 3.3 v i/o with 5 v tolerant inputs; 1.8 v core voltage applications ? pbx and ip-pbx ? small and medium digital switching platforms ? remote access servers and concentrators ? wireless base stations and controllers ? multi service access platforms ? digital loop carriers ? computer telephony integration february 2004 ordering information ZL50017gac 256-ball pbga ZL50017qcc 256-lead lqfp -40 c to +85 c ZL50017 1 k digital switch data sheet figure 1 - ZL50017 functional block diagram data memory input timing te s t p o r t s/p converter stio[15:0] ode reset v ss v dd_io v dd_core fpi cki mot_intel ds _rd cs d[15:0] a[13:0] tms tdi tdo tck trst sti[15:0] p/s converter dta _rdy r/w _wr connection memory internal registers µprocessor interface
ZL50017 data sheet 2 zarlink semiconductor inc. description the ZL50017 is a maximum 1024 x 1024 ch annel non-blocking digital time divisi on multiplex (tdm) switch. it has sixteen input streams (sti0 - 15) and sixteen output streams (stio0 - 15). the device can switch 64 kbps and nx64 kbps tdm channels from any input stream to any out put stream. all of the input and output streams operate at the same data rate and can be programmed at any of the following data rates: 2.048 mbps, 4.096 mbps, 8.192 mbps or 16.384 mbps. the output streams can be configur ed to operate in bi-directional mode, in which case sti0 - 15 will be ignored. the device contains two types of internal memory - data memory and connection memory. there are three modes of operation - connection mode, message mode and high impedance mode. in connection mode, the contents of the connection memory define, for each output stream and channel, the source stream and channel (the actual data to be output is stored in the data memory). in message mode, the connection memory is used for the storage of microprocessor data. using zarlin k's message mode capability, microprocessor data can be broadcast to the data output streams on a per-channel basis. this feature is useful for transfer ring control and status information for external circuits or other tdm devi ces. in high impedance mode the selected output channel can be put into a high impedance state. the configurable non-multiplexed micr oprocessor port allows users to program various device operating modes and switching configurations. users ca n employ the microprocessor port to pe rform register read/ write, connection memory read/write and data memory read operations. the port is configurable to interface with either motorola or intel-type microprocessors. the device also supports the mandatory requirements of the ieee-1149.1 (jtag) st andard via the test port. ZL50017 data sheet table of contents 3 zarlink semiconductor inc. 1.0 pinout diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 bga pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 qfp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.0 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.0 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.0 data rates and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 input clock (cki) and input frame pulse (fpi) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 st-bus and gci-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 data input delay and data output advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 input bit delay programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 output advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 fractional output bit advancement programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 constant delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.0 connection memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.0 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1 memory block programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.0 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.2 device initialization on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.0 jtag port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.3 test data registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.4 bsdl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 12.0 register address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13.0 detailed register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.0 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.1 memory address mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.2 connection memory low (cm_l) bit assi gnment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.0 dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.0 ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50017 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - ZL50017 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - ZL50017 256-ball 17 mm x 17 mm pbga (as viewed through top of package) . . . . . . . . . . . . . . . . . . . 6 figure 3 - ZL50017 256-lead 28 mm x 28 mm lqfp (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4 - input timing when ckin1 - 0 bits = ?10? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5 - input timing when ckin1 - 0 bits = ?01? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 - input timing when ckin1 - 0 = ?00? in the cr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7 - input bit delay timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 - input bit sampling point programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 - input bit delay and factional sampling point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10 - output bit advancement timing diagram (st-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11 - output fractional bit advancem ent timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 - data throughput delay for variable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 - data throughput delay for constant delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15 - motorola non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16 - motorola non-multiplexed bus timing - write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 17 - intel non-multiplexed bus timing - read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 18 - intel non-multiplexed bus timing - write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19 - jtag test port timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20 - frame pulse input and clock input timing diagram (st-bus). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21 - frame pulse input and clock input timing diagram (gci-bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22 - st-bus input and output timing diagram when o perated at 2, 4, 8 and 16 mbps . . . . . . . . . . . . . . 46 figure 23 - gci-bus input and output timi ng diagram when operated at 2, 4, 8 and 16 mbps . . . . . . . . . . . . . 47 ZL50017 data sheet list of tables 5 zarlink semiconductor inc. table 1 - cki and fpi configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 - delay for variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3 - connection memory low after block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 4 - address map for registers (a13 = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5 - control register (cr) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6 - internal mode selection register (ims) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7 - software reset register (srr) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 8 - data rate selection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9 - internal flag register (ifr) bits - read only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 - stream input control register 0 - 15 (sicr0 - 15) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11 - stream output control register 0 - 15 (socr0 - 15) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12 - address map for memory locations (a13 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13 - connection memory low (cm_l) bit assignment when cmm = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14 - connection memory low (cm_l) bit assignment when cmm = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ZL50017 data sheet 6 zarlink semiconductor inc. 1.0 pinout diagrams 1.1 bga pinout figure 2 - ZL50017 256-ball 17 mm x 17 mm pbga (as viewed through top of pa ckage) 12345678 910111213141516 a v ss nc nc nc nc nc nc nc nc nc nc nc nc nc nc v ss a b nc sti10 sti5 sti4 nc sti0 nc nc v dd_ core fpi cki ic_open ic_open ic_gnd ode nc b c nc sti9 v ss sti7 sti6 sti1 nc nc v ss ic_open ic_open ic_open ic_gnd v ss stio15 nc c d nc sti11 v dd_io sti3 sti2 nc nc nc nc v ss nc ic_gnd stio13 v dd_io stio14 nc d e nc sti14 sti8 v dd_io v ss v dd_ core nc nc nc nc v dd_ core v ss v dd_io stio12 nc nc e f nc sti15 sti12 sti13 v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io ic_open nc nc nc f g nc reset ic_gnd ic_open tdo v dd_io v ss v ss v ss v ss v dd_io a12 a13 nc nc nc g h nc v ss v ss v dd_ core nc v ss v ss v ss v ss v ss a7 a9 a10 nc a11 nc h j nc v dd_io v dd_io v ss v ss nc v ss v ss v ss v ss a3 a4 a5 a8 a6 nc j k nc v ss tms v ss v dd_ core v dd_io v ss v ss v ss v ss v dd_io ic_open a0 a2 a1 nc k l nc v dd_ core trst tck v dd_io v dd_ core v dd_ core v ss v ss v dd_ core v dd_ core v dd_io stio10 stio11 stio9 nc l m nc nc tdi d0 v ss v dd_ core v dd_ core d6 d10 v dd_ core v dd_ core v ss mot _intel ic_open stio8 nc m n nc nc v dd_io stio0 nc d1 d5 d7 d11 d13 r/w _wr dta _ rdy stio4 v dd_io nc nc n p nc nc v ss stio1 stio3 nc d3 d8 d14 nc stio5 nc nc v ss nc nc p r nc nc nc stio2 nc d2 d4 d9 d12 d15 cs ds _rd ic_open stio6 stio7 nc r t v ss nc nc nc nc nc nc nc nc nc nc nc nc nc nc v ss t 12345678 910111213141516 note: a1 corner id entified by metallized marking. note: pinout is shown as viewed through top of package. ZL50017 data sheet 7 zarlink semiconductor inc. 1.2 qfp pinout figure 3 - ZL50017 256-lead 28 mm x 28 mm lqfp (top view) 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 22 24 26 28 30 20 18 16 14 12 10 8 6 4 2 120 102 104 106 108 110 114 116 118 112 52 54 56 58 60 50 48 46 44 42 40 38 36 34 32 100 82 84 86 88 90 94 96 98 92 80 66 68 70 74 76 78 72 132 134 136 138 140 142 144 146 148 150 cki fpi ic_open ic_open ic_open ic_open ic_gnd vdd_io vss ic_gnd ode vdd_io nc nc nc nc 62 64 122 124 126 128 182 184 186 188 190 nc nc vss vdd_io sti_7 sti_6 sti_3 sti_2 sti_1 sti_0 nc vss nc nc nc nc nc nc vss nc nc sti_5 sti_4 vdd_io nc nc vss vdd_core nc vss vdd_io nc nc vss vdd_core nc vdd_io nc nc nc nc nc nc vdd_io trst tck tms vss vdd_core vss vdd_core vss vss nc vdd_io vdd_core vss vss nc vdd_io vss vdd_core vss vss vdd_core tdo reset ic_open ic_gnd vss vdd_io sti_15 sti_14 sti_11 sti_10 sti_9 sti_8 nc nc nc vss tdi nc vdd_io nc 202 220 218 216 214 212 208 206 204 210 222 240 238 236 234 232 228 226 224 230 242 256 254 252 248 246 244 250 200 198 196 194 vss sti_13 sti_12 nc nc nc nc vdd_io vss stio_0 stio_1 stio_2 stio_3 nc nc nc nc vdd_io vss d0 vdd_core vss d1 d2 d3 d4 d5 d7 d8 d9 d6 vdd_io vss d10 vdd_core vss d11 d12 d13 d14 d15 r/w _wr cs mot_intel ds _rd nc dta _rdy ic_open vdd_core vss ic_open vdd_io vss stio_4 stio_5 stio_6 stio_7 nc nc nc nc vdd_io vss nc nc nc nc nc vdd_io vss stio_8 stio_9 stio_10 stio_11 nc nc nc nc vdd_io ic_open vss vdd_core vss a0 a1 a2 a3 a4 a7 a6 a5 a11 a10 a9 a8 vdd_core vss a13 a12 ic_open vdd_io vss nc nc nc nc nc nc nc vdd_core vss ic_gnd vdd_io vss stio_12 stio_13 stio_14 stio_15 nc nc nc nc vdd_io vss nc nc nc nc nc nc nc nc nc nc nc vss vdd_core vss vss vdd_io nc nc nc nc vss nc nc nc 192 130 nc nc nc nc nc nc ic_open ZL50017 data sheet 8 zarlink semiconductor inc. 2.0 pin description pbga pin number lqfp pin number pin name description b9, e6, e11, f6, f7, f10, f11, h4, k5, l2, l6, l7, l10, l11, m6, m7, m10, m11 19, 33, 45, 83, 95, 109, 146, 157, 173, 213, 217, 224, 231, 233 v dd_core power supply for the core logic: +1.8 v d3, d14, e4, e13, f5, f12, g6, g11, j2, j3, k6, k11, l5, l12, n3, n14 5, 15, 29, 49, 57, 69, 79, 101, 113, 121, 133, 143, 160, 169, 177, 186, 195, 207, 220, 226, 241, 249 v dd_io power supply for i/o: +3.3 v a1, a16, c3, c9, c14, d10, e5, e12, f8, f9, g7, g8, g9, g10, h2, h3, h6, h7, h8, h9, h10, j4, j5, j7, j8, j9, j10, k2, k4, k7, k8, k9, k10, l8, l9, m5, m12, p3, p14, t1, t16 8, 17, 21, 31, 35, 47, 50, 60, 71, 81, 85, 97, 103, 111, 114, 123, 142, 145, 147, 156, 158, 162, 171, 175, 178, 188, 199, 209, 214, 216, 218, 222, 223, 228, 230, 232, 235, 242, 251 v ss ground k3 234 tms test mode select (5 v-tolerant input with internal pull-up) jtag signal that contro ls the state transitions of the tap controller. this pin is pulled high by an internal pull-up resistor when it is not driven. l4 238 tck test clock (5 v-tolerant schmitt-triggered input with internal pull-up) provides the clock to the jtag test logic. ZL50017 data sheet 9 zarlink semiconductor inc. l3 239 trst test reset (5 v-tolerant input with internal pull-up) asynchronously initializes t he jtag tap controller by putting it in the test-logic-re set state. this pin should be pulsed low during power-up to ensure that the device is in the normal functional mode. when jtag is not being used, this pin should be pulled low during normal operation. m3 240 tdi test serial data in (5 v-tolerant input with internal pull-up) jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up resistor when it is not driven. g5 212 tdo test serial data out (5 v-tolerant three-state output) jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag is not enabled. b13, c11, c12, f13, g4, k12, m14, r13 46, 48, 80, 105, 150, 151, 210, 149 ic_open internal test mode (5 v-tolerant input with internal pull-down) these pins may be left unconnected. g3, d12,c13 b14 144, 107, 148, 208 ic_gnd internal test mode enable (5 v-tolerant input) these pins must be low. pbga pin number lqfp pin number pin name description ZL50017 data sheet 10 zarlink semiconductor inc. a8, a9, a14, a15, b12, c10, e10, m2, n2, p2, p16, r2, r16, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, d16, e16, c16, b16, a13, a12, a10, a11, n1, m1, p1, r1, t2, t3, t5, t4, n16, m16, l16, k16, h16, j16, g16, f16,d9, e8, c8, e7, d6, h5, p10, g15, g14, e15, f14, h14, d11, f15, b7, c7, b5, j6, r3, p6, r5, n5, p12, n15, p13, p15, e1, d1, g1, f1, j1, h1, k1, l1, a7, a5, a6, a4, a3, a2, c1, b1, e9, d8, b8, d7 61, 62, 63, 64, 65, 66, 67, 68, 134, 135, 136, 137, 138, 139, 140, 152, 153, 215, 219, 225, 229, 236, 237, 125, 126, 127, 128, 129, 130, 131, 132, 253, 254, 255, 256, 1, 2, 3, 4, 75, 76, 77, 78, 119, 120, 122, 124,159, 163, 165, 167, 176, 221, 43, 102, 106, 110, 112, 100, 104, 108, 170, 172, 174, 227, 11, 12, 13, 14, 55, 56, 58, 59, 243, 244, 245, 246, 247, 248, 250, 252, 189, 190, 191, 192, 193, 194, 196, 197, 161, 164, 166, 168 nc no connect these pins must be left unconnected. pbga pin number lqfp pin number pin name description ZL50017 data sheet 11 zarlink semiconductor inc. b10 155 fpi st-bus/gci-bus frame pulse input (5 v-tolerant schmitt-triggered input) this pin accepts the frame pulse which stays active for 61 ns, 122 ns or 244 ns at the frame boundary. the frame pulse frequency is 8 khz. the frame pulse associated with the cki must be applied to this pin. by default, the device accepts a negative frame pulse in st-bus format, but it can accept a positive frame pulse instead if the fpinp bit is set high in the control register (cr). it can acc ept a gci-formatted frame pulse by programming the fpinpos bit in the control register (cr) to high. b11 154 cki st-bus/gci-bus clock input (5 v-tolerant schmitt-triggered input) this pin accepts a 4.096 mhz, 8.192 mhz or 16.384 mhz clock. the clock frequency applied to this pin must be twice the highest input or output data rate. the exception is, when data is running at 16.384 mbps, a 16.384 mhz clock must be used. by default, the clock falli ng edge defines the input frame boundary, but the device allows the clock rising edge to define the frame boundary by programming the ckinp bit in the control register (cr). b6, c6, d5, d4, b4, b3, c5, c4, e3, c2, b2, d2, f3, f4, e2, f2 179, 180, 181, 182, 183, 184, 185, 187, 198, 200, 201, 202, 203, 204, 205, 206 sti0 - 15 serial input streams 0 to 15 (5 v-tolerant inputs with internal pull-downs) the data rate of all the i nput streams are programmed through the ?data rate selection register? on page 30. in the 2.048 mbps mode, these pins accept serial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, these pins accept serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, these pins accept serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.384 mbps mode, these pins accept serial tdm data streams at 16.384 mbps with 256 channels per frame. pbga pin number lqfp pin number pin name description ZL50017 data sheet 12 zarlink semiconductor inc. n4, p4, r4, p5, n13, p11, r14, r15, m15, l15, l13, l14, e14, d13, d15, c15 6, 7, 9, 10, 51, 52, 53, 54, 70, 72, 73, 74, 115, 116, 117, 118 stio 0 - 15 serial output streams 0 to 15 (5 v-tolerant slew-rate-limited three-st ate i/os with enabled internal pull-downs) the data rate of all the out put streams are programmed through the ?data rate selection register? on page 30. in the 2.048 mbps mode, thes e pins output serial tdm data streams at 2.048 mbps with 32 channels per frame. in the 4.096 mbps mode, thes e pins output serial tdm data streams at 4.096 mbps with 64 channels per frame. in the 8.192 mbps mode, thes e pins output serial tdm data streams at 8.192 mbps with 128 channels per frame. in the 16.384 mbps mode, these pins output serial tdm data streams at 16.384 mbps with 256 channels per frame.these output streams can be used as bi-directionals by programming bdh (bit 7) and bdl (bit 6) of internal mode selection (ims) register. b15 141 ode output drive enable (5 v-tolerant input with internal pull-up) this is the output enable control for stio0 - 15. when it is high, stio0 - 15 are enabled. when it is low, stio0 - 15 are tristated. m4, n6, r6, p7, r7, n7, m8, n8, p8, r8, m9, n9, r9, n10, p9, r10 16, 18, 20, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 36, 37, 38 d0 - 15 data bus 0 to 15 (5 v-tolerant slew-rate-limited three-state i/os) these pins form the 16-bit data bus of the microprocessor port. n12 44 dta _rdy data transfer acknowledgment_ready (5 v-tolerant three-state output) this active low output indicates that a data bus transfer is complete for the motorola interface. for the intel interface, it indicates a transfer is completed when this pin goes from low to high. an external pull-up resistor must hold this pin at high level for the motorola mode. an external pull-down resistor must hold this pin at low level for the intel mode. r11 40 cs chip select (5 v-tolerant input) active low input used by the motorola or intel microprocessor to enable the microprocessor port access. n11 39 r/w _wr read/write_write (5 v-tolerant input) this input controls the direct ion of the data bus lines (d0 - 15) during a microprocesso r access. for the motorola interface, this pin is set high and low for the read and write access respectively. for the intel interface, a write access is indicated when this pin goes low. pbga pin number lqfp pin number pin name description ZL50017 data sheet 13 zarlink semiconductor inc. 3.0 device overview the device has sixteen st-bus/gci-bus inputs (sti0 - 15) and sixteen st-bus/gci-bus outputs (stio0 - 15). stio0 - 15 can also be configured as bi-directional pins, in which case sti0 - 15 will be ignored. it is a non-blocking digital switch with 1024 64 kbps channels. the st-bus /gci-bus inputs and outputs accept serial input data streams with data rates of 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps. by using zarlink?s message mode capability, microproc essor data stored in the connection memory can be broadcast to the output streams on a pe r-channel basis. this feature is usef ul for transferring control and status information for external circuits or other st-bus/gci-bus devices. the device uses the st-bus/gci-bus input frame pulse (f pi) and the st-bus/gci-bus input clock (cki) to define the input frame boundary and timing for sampling the st-bus/gci-bus input st reams with various data rates. the output data streams will be driven by and have their timing defined by fpi and cki. a motorola or intel compatible non-multiplexed microprocessor port allows users to program the device to operate in various modes under different switching configurations. us ers can use the microprocessor port to perform internal register and memory r12 42 ds _rd data strobe_read (5 v-tolerant input) this active low input works in conjunction with cs to enable the microprocessor port read and write operations for the motorola interface. a read access is indicated when it goes low for the intel interface. k13, k15, k14, j11, j12, j13, j15, h11, j14, h12, h13, h15, g12, g13 82, 84, 86, 87, 88, 89, 90, 91, 92, 93, 94, 96, 98, 99 a0 - 13 address 0 to 13 (5 v-tolerant inputs) these pins form the 14-bit address bus to the internal memories and registers. m13 41 mot_intel motorola_intel (5 v-tolerant input with internal pull-up) this pin selects the motorola or intel microprocessor interface to be connected to the device. when this pin is unconnected or connected to high, motorola interface is assumed. when this pin is connected to ground, intel interface should be used. g2 211 reset device reset (5 v-tolerant input with internal pull-up) this input (active low) puts the device in its reset state that disables the stio0 - 31 drivers. it also preloads registers with default valu es and clears all internal counters. to ensure proper reset action, the reset pin must be low for longer than 1 s. upon releasing the reset signal to the device , the first microprocessor access cannot take place for at least 500 s due to the time required to stabilize the device from the power-down state. refer to section section 10.2 on page 24 for details. pbga pin number lqfp pin number pin name description ZL50017 data sheet 14 zarlink semiconductor inc. read and write operations. the micropr ocessor port has a 16-bit data bus, a 14-bit address bus and six control signals (mot_intel , cs , ds _rd , r/w _wr and dta _rdy). the device supports the mandatory requirements of the ieee-1149.1 (j tag) standard via the test port. 4.0 data rates and timing the ZL50017 has 16 serial data inputs and 16 serial data outputs. all streams are programmed to operate at 2.048 mbps, 4.096 mbps, 8.192 mbps or 16.384 mbps. dependi ng on the data rate there will be 32 channels, 64 channels, 128 channels or 256 channels, respectively, during a 125 s frame. the output streams can be programmed to operate as bi-directional streams. by setting bdl (bit 6) in the internal mode selection (ims) register, the inpu t streams 0 - 15 (sti0 - 15) are internally tied low, and the output streams 0 - 15 (stio0 - 15) are set to operate in a bi-directional mode.the input data rate is set on a per-stream basis by programming stin[n]dr3 - 0 (bits 3 - 0) in the stream i nput control register 0 - 15 (sicr0 - 15). the output data rate is set on a per-stream basis by pr ogramming sto[n]dr3 - 0 (bits 3 - 0) in the stream output control register 0 - 15 (socr0 - 15). the output data rates do not have to match or follow the input data rates. the maximum number of channels switched is limited to 1024 channels. if all 16 input streams were operating at 8.192 mbps (128 channels per stream), this would result in 2048 channels. memory limitations prevent the device from operating at this capacity. a maximum capacity of 1024 channels will occur if four streams are operating at 16.384 mbps, eight streams are operating at 8.192 mbps or all sixteen streams are operating at 4.096 mbps. with all streams operating at 2.048 mbps, the capacity will be reduced to 512 c hannels. it should be noted that only full streams can be enabled, the device does not allow part ial streams configurati on (i.e., cannot have al l the streams operating at 16.384 mbps but only access the half the channels). 4.1 input clock (cki) and input frame pulse (fpi) timing the frequency of the input clock (cki) for the ZL50017 must be at least twice the input/output data rate. for example, if the input/output data rate is 8.192 mbps, the input clock, cki, must be 16.384 mhz. following the example above, if the input/output data rate is 4.096 mb ps, the input clock, cki, must be 8.192 mhz.the only exception to this is for 16.384 mbps input/output data. in this case, the input clock, cki, is equal to the data rate. the input frame pulse, fpi, must always follow cki. ckin 1 - 0 (bits 6 - 5) in the control register (cr) are used to program the width of the input fr ame pulse and the frequency of the input clock supplied to the device. the ZL50017 accepts positive and negative st-bus/gci-bus input clock and input frame pulse formats via the programming of ckinp (bit 8) and fpinp (bit 7) in the control register (cr). by def ault, the device accepts the negative input clock format and st-bus format frame pulses . however, the switch can al so accept a positive-going clock format by programming ckinp (bit 8) in the cont rol register (cr). a gci-bus format frame pulse can be used by programming fpinpos (bit 9) and fpin p (bit 7) in the co ntrol register (cr). highest input or output data rate ckin 1-0 bits input clock rate (cki) input frame pulse (fpi) 16.384 mbps or 8.192 mbps 00 16.384 mhz 8 khz (61 ns wide pulse) 4.096 mbps 01 8.192 mhz 8 khz (122 ns wide pulse) 2.048 mbps 10 4.096 mhz 8 khz (244 ns wide pulse) table 1 - cki and fpi configurations ZL50017 data sheet 15 zarlink semiconductor inc. figure 4 - input timing when ckin1 - 0 bits = ?10? in the cr figure 5 - input timing when ckin1 - 0 bits = ?01? in the cr fpi (244 ns) fpinp = 0 fpinpos = 0 fpi (244 ns) fpinp = 1 fpinpos = 0 fpi (244 ns) fpinp = 0 fpinpos = 1 fpi (244 ns) fpinp = 1 fpinpos = 1 cki (4.096 mhz) ckinp = 0 cki (4.096 mhz) ckinp = 1 76 1 0 0 7 sti (2.048 mbps) channel 0 channel 31 st-bus gci-bus fpi (122 ns) fpinp = 0 fpinpos = 0 fpi (122 ns) fpinp = 1 fpinpos = 0 fpi (122 ns) fpinp = 0 fpinpos = 1 fpi (122 ns) fpinp = 1 fpinpos = 1 cki (8.192 mhz) ckinp = 0 cki (8.192 mhz) ckinp = 1 sti (4.096 mbps) channel 0 channel 63 6 54 1 0 2 76 7 1 0 st-bus gci-bus ZL50017 data sheet 16 zarlink semiconductor inc. figure 6 - input timing when ckin1 - 0 = ?00? in the cr 4.2 st-bus and gci-bus timing the ZL50017 is capable of operating us ing either the st-bus or gci-bus standards. by default, the ZL50017 is configured for st-bus input and output timing. to set the in put timing to conform to the gci-bus standard, fpinpos (bit 9) and fpinp (bit 7) in the control register (cr) must be set. 5.0 data input delay and data output advancement various registers are provi ded to adjust the input delay and output advancement for each input and output data stream. the input bit delay and output bit advancement ca n vary from 0 to 7 bits for each individual stream. if input delay of less than a bit is desired, different sampling points can be used to handle the adjustments. the sampling point can vary from 1/4 to 4/ 4 with a 1/4-bit increment for all inpu t streams. by defaul t, the sampling point is set to the 3/4-bit location. the fractional output bit advancement can va ry from 0 to 3/4 bits, again with a 1/4 bit increment. by default, there is 0 output bit advancement. although input delay or output advancem ent features are available on stream s which are operating in bi-directional mode it is not recommended, as it can easily cause bus co ntention. if users require this function, special attention must be given to the timing to en sure contention is minimized. fpi (61ns) fpinp = 0 fpinpos = 0 fpi (61ns) fpinp = 1 fpinpos = 0 fpi (61ns) fpinp = 0 fpinpos = 1 fpi (61ns) fpinp = 1 fpinpos = 1 cki (16.384 mhz) ckinp = 0 cki (16.384 mhz) ckinp = 1 sti (8.192 mbps) channel 0 channel n = 127 6 5 4 3 2 1 3 2 1 0 5 4 7 6 5 7 1 0 sti (16.384 mbps) channel 0 channel n = 255 6 7 4 5 2 3 0 1 6 7 4 5 2 3 2 3 0 1 6 7 4 5 2 3 6 7 4 5 2 3 0 1 2 3 0 1 st-bus gci-bus ZL50017 data sheet 17 zarlink semiconductor inc. 5.1 input bit delay programming the input bit delay programming feature provides us ers with the flexibility of hand ling different wire delays when designing with source str eams for different devices. by default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming st-bus formatting). the input delay is enabled by stin[n]bd2-0 (bits 8 - 6) in the stream input control register 0 - 15 (sicr0 - 15) as descri bed in section 10 on page 31. the input bit delay can range from 0 to 7 bits. figure 7 - input bit delay timing diagram (st-bus) fpi sti[n] bit delay = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel sti[n] bit delay = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 4 3 last channel bit delay = 1 5 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. ZL50017 data sheet 18 zarlink semiconductor inc. 5.2 input bit sampling point programming in addition to the input bit delay featur e, the ZL50017 allows users to change the sampling point of the input bit by programming stin[n]smp 1-0 (bits 5 - 4) in the stream input control register 0 - 15 (sicr0 - 15). for input streams the default sampling point is at 3/4 bit and users can change the sampling point to 1/4, 1/2, 3/4 or 4/4 bit position. figure 8 - input bit sampling point programming fpi sti[n] stin[n]smp1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel sampling point = 1/4 bit sti[n] stin[n]smp1-0 = 10 2, 4 or 8 mbps stin[n]smp1-0 = 00 16 mbps - default channel 0 last channel sampling point = 1/2 bit sti[n] stin[n]smp1-0 = 00 2, 4 or 8 mbps - default channel 0 last channel sampling point = 3/4 bit 1 0 7 6 2 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps mode respectively sti[n] stin[n]smp1-0 = 11 2, 4 or 8 mbps stin[n]smp1-0 = 10 16 mbps channel 0 last channel sampling point = 4/4 bit 5 1 0 7 6 5 1 0 7 6 5 1 0 7 6 2 5 ZL50017 data sheet 19 zarlink semiconductor inc. the input delay is controlled by stin[n]bd2-0 (bits 8 - 6) to control the bit shift and stin[n]smp1 - 0 (bits 5 - 4) to control the sampling point in the stream i nput control register 0 - 15 (sicr0 - 15). figure 9 - input bit delay and factional sampling point 5.3 output advancement programming this feature is used to advance the output data of indi vidual output streams with respect to the input frame boundary. each output stream has its own bit advancem ent value which can be programmed in the stream output control register 0 - 15 (socr0 - 15). by default, all output streams have zero bit advancement such that bit 7 is the first bit that appears after the input frame boundary (assuming st-bus format ting). the output advancement is enab led by sto[n]ad 2 - 0 (bits 6 - 4) of the stream output contro l register 0 - 15 (socr0 - 15) as described in section 11 on page 32. the output bit advancement can vary from 0 to 7 bits. nominal channel n+1 boundary 7 6 5 4 3 2 1 0 7 0 000 01 000 10 000 00 (default) 000 11 001 01 001 10 001 00 001 11 010 01 010 10 010 00 010 11 011 01 011 10 011 00 011 11 111 00 111 10 111 01 110 11 110 00 110 10 110 01 101 11 101 00 101 10 101 01 100 11 100 00 100 10 100 01 111 11 the first 3 bits represent stin[n]bd2 - 0 for setting the bit delay. the second set of 2 bits represent stin[n]smp1 - 0 for setting the sampling point offset. sti[n] nominal channel n boundary example: with a setting of 011 10 the offs et will be 3 bits at a 1/2 sampling point. note: italic settings can be used in 16 mbps mode (1/2 and 4/4 sampling point). ZL50017 data sheet 20 zarlink semiconductor inc. figure 10 - output bit advancement timing diagram (st-bus) 5.4 fractional output bit advancement programming in addition to the output bit advanceme nt, the device has a fractional output bit advancement feature that offers better resolution. the fractional output bit advancement is useful in compensating for varying parasitic load on the serial data output pins. by default all of the streams have zero fr actional bit advancement such that bit 7 is the first bit that appears after the output frame boundary. the fractional output bit advancement is enabled by sto[n]fa 1 - 0 (bits 8 - 7) in the stream output control register 0 - 15 (socr0 - 15). fo r all streams the fractional bi t advancement can vary from 0, 1/4, 1/2 to 3/4 bits. figure 11 - output fractional bit advancement timing diagram (st-bus) fpi stio[n] bit adv = 0 (default) channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 channel 2 2 1 0 4 3 last channel stio[n] bit adv = 1 channel 0 7 channel 1 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 channel 2 2 1 0 3 last channel bit advancement = 1 note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 2 1 fpi stio[n] sto[n]fa1-0 = 00 (default) channel 0 7 last channel stio[n] sto[n]fa1-0 = 01 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 1/4 bit 6 5 2 1 0 stio[n] sto[n]fa1-0 = 10 (2, 4 or 8 mbpa) sto[n]fa1-0 = 01 (16mbps) channel 0 last channel fractional bit advancement = 1/2 bit stio[n] sto[n]fa1-0 = 11 (2, 4 or 8 mbps) channel 0 last channel fractional bit advancement = 3/4 bit note: last channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 mbps modes respectively. 7 6 5 1 0 7 6 5 1 0 7 6 5 1 0 4 4 4 ZL50017 data sheet 21 zarlink semiconductor inc. 6.0 data delay through the switching paths the switching of information from the i nput serial streams to the output seri al streams results in a throughput delay. the device can be programmed to perform timeslot in terchange functions with different throughput delay capabilities on a per-channel basis. for voice applications , select variable throughput delay to ensure minimum delay between input and output data. in wideband data applic ations, select constant delay to maintain the frame integrity of the information through the switch. the delay through the device varies according to the type of throughput delay selected by the v/c (bit 14) in the connection memory low when cmm = 0. 6.1 variable delay mode variable delay mode causes the output channel to be transmi tted as soon as possible. this is a useful mode for voice applications where the minimum throughput delay is mo re important than frame integrity. the delay through the switch can vary from 7 channels to 1 frame + 7 chan nels. to set the device into variable delay mode, varen (bit 4) in the control register (cr) must be set before v/c (bit 14) in the connection memory low when cmm = 0. if the varen bit is not set and the device is programmed for variable delay mode, the information read on the output stream will not be valid. in variable delay mode, the delay depends on the combination of the source and destination channels of the input and output streams. for example, if stream 4 channel 2 is switched to stream 5 channel 9 with variable dela y, the data will be output in the same 125 s frame. contrarily, if stream 6 channel 1 is sw itched to stream 9 channel 3, the information will appear in the following frame. figure 12 - data throughput delay for variable delay m = input channel number n = output channel number n-m <= 0 0 < n-m < 7 n-m = 7 n-m > 7 stio < sti stio >= sti t = delay between input and output 1 frame - (m-n) 1 frame + (n-m) n-m table 2 - delay for variable delay mode l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 sti4 ch2 stio5 ch9 sti6 ch1 stio9 ch3 frame n frame n + 1 l = last channel = 31, 63, 127 or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps respectively. ZL50017 data sheet 22 zarlink semiconductor inc. 6.2 constant delay mode in this mode, frame integrity is maintained in all switchin g configurations. the delay though the switch is 2 frames - input channel + output channel. this can re sult in a minimum of 1 frame + 1 chan nel delay if the last channel on a stream is switched to the first channel of a stream. the maximum delay is 3 frames - 1 channel. this occurs when the first channel of a stream is switched to the last channel of a stream. the cons tant delay mode is available for all output channels. the data throughput delay is expressed as a function of st-bus/gci-bus frames, input channel number (m) and output channel number (n). the data throughput delay (t) is: t = 2 frames + (n - m) the constant delay mode is controlled by v/c (bit 14) in the connection memory low when cmm = 0. when this bit is set low, the channel is in constant delay mode. if vare n (bit 4) in the control register (cr) is set (to enable variable throughput dela y on a chip-wide basis), the de vice can still be programmed to operate in c onstant delay mode. figure 13 - data throughput delay for constant delay 7.0 connection memory description the connection memory consists of two blocks, connection memory low (cm_l). the cm_l is 16 bits wide and is used for channel switching and other special modes. each connection memory location of the cm_l or cm_h can be read or written via the 16 bit microprocessor port within one microprocessor access cycle. see table 12 on page 33 for the address mapping of the connection memory. an y unused bits will be reset to zero on the 16-bit data bus. for the normal channel switching operat ion, cmm (bit 0) of the connection memory low (cm_l) is programmed low. sca7 - 0 (bits 8 - 1) indicate the source (input) chann el address and ssa4 - 0 (bits 13 - 9) indicate the source (input) stream address. when cmm (bit 0) of the connection memory low (cm_l) is programmed high, the ZL50017 will operate in one of the special modes descr ibed in table 14 on page 35. when the per-channel message mode is enabled, msg7 - 0 (bit 10 - 3) in the co nnection memory low (cm_l) will be output via the serial data stream as message output data. l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 l-2 l-1 ch0 ch1 ch2 ch3 sti stio sti stio l = last channel = 31, 63, 127 or 255 for 2.048 mbps, 4.096 mbps, 8.192 mbps and 16.384 mbps respectively. frame n frame n + 1 frame n + 2 ZL50017 data sheet 23 zarlink semiconductor inc. 8.0 connection memory block programming this feature allows for fast initialization of the conne ction memory after power up. 8.1 memory block programming procedure 1. set mbpe (bit 3) in the control register (cr) from low to high. 2. configure bpd2 - 0 (bits 3 - 1) in the internal mode sele ction (ims) register to the desired values to be loaded into cm_l. 3. start the block progra mming by setting mbps (bit 0) in the internal mode selection register (ims) high. the val- ues stored in bpd2 - 0 will be loaded into bits 2 - 0 of all cm_l positions. the remaining cm_l locations (bits 15 - 3). the following tables show the resulting values that ar e in the cm_l and cm_h connection memory locations. it takes at least tw o frame periods (250 s) to complete a block program cycle. mbps (bit 0) in the control register (cr) will automatically reset to a low position after the block programming process has completed. mbpe (bit 3) in the internal mode sele ction (ims) register must be cleared from high to lo w to terminate the block programming process. this is not an automatic acti on taken by the device and must be performed manually. note : once the block program has been initiated, it can be terminated at any time prio r to completion by setting mbps (bit 0) in the control register ( cr) or mbpe (bit 3) in the internal mo de selection (ims) register to low. 9.0 microprocessor port the device provides access to the internal regi sters, connection memories and data memories via the microprocessor port. the microprocessor port is capable of supporting both motorola and intel non-multiplexed microprocessors. the microproces sor port consists of a 16-bit parallel data bus (d15 - 0), 14 bit address bus (a13 - 0) and six control signals (mot_intel , cs , ds _rd , r/w _wr and dta _rdy). the data memory can only be read from the microprocessor port. for a data memory read operation, d7 - 0 will be used and d15 - 8 will output zeros. for a cm_l read or write oper ation, all bits (d15 - 0) of the data bus will be used. fo r a cm_h write operation, d4 - 0 of the data bus must be configured and d15 - 5 are ignored. d15 - 5 must be driven either high or low. for a cm_h read operation, d4 - 0 will be used and d15 - 5 will output zeros. refer to figure 15 on page 38, figure 16 on page 39, figure 17 on page 40 and figure 18 on page 41 for the microprocessor timing. bit1514131211109876543 2 1 0 value0000000000000bpd2bpd1bpd0 table 3 - connection memory low after block programming ZL50017 data sheet 24 zarlink semiconductor inc. 10.0 device reset and initialization the reset pin is used to reset the ZL50017. when this pin is low, the following functions are performed: ? synchronously puts the microprocessor port in a reset state ? tristates the stio0 - 15 outputs ? preloads all internal registers with their default values (refer to the individual registers for default values) ? clears all internal counters 10.1 power-up sequence the recommended power-up sequence is for the v dd_io supply (normally +3.3 v) to be established before the power-up of the v dd_core supply (normally +1.8 v). the v dd_core supply may be powered up at the same time as v dd_io , but should not ?lead? the v dd_io supply by more than 0.3 v. 10.2 device initialization on reset upon power up, the ZL50017 should be initialized as follows: ? set the ode pin to low to disable the stio0 - 15 outputs ? set the trst pin to low to disable the jtag tap controller ? reset the device by pulsing the reset pin to zero for longer than 1 s ? after releasing the reset pin from low to high, wait for a certain period of time (see note below) for the device to stabilize from the power down state before the first microprocessor port access can occur ? wait at least 500 s prior to the next microport access (see note below) ? use the block programming mode to initialize the connection memory ? release the ode pin from low to high after the connection memory is programmed note : if cki is 16.384 mhz, the waiting time is 500 s; if cki is 8.192 mhz, the waiting time is 1 ms; if cki is 4.096 mhz, the waiting time is 2 ms. 10.3 software reset in addition to the hardware reset from the reset pin, the device can also be reset by using software reset srstsw (bit 1) in the software reset register (srr). 11.0 jtag port the jtag test port is implemented to meet the mandat ory requirements of the ieee -1149.1 (jtag) standard. the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. 11.1 test access port (tap) the test access port (tap) accesses the ZL50017 test func tions. it consists of three input pins and one output pin as follows: ? test clock input (tck) - tck provides the clock for the test logic. tck does not interfere with any on-chip clock and thus remains independent in the functional mode. tck permits shifting of test data into or out of the boundary-scan register cells concurrently with t he operation of the device and without interfering with the on-chip logic. ZL50017 data sheet 25 zarlink semiconductor inc. ? test mode selection inputs (tms) - the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is no t driven from an external source. ? test data input (tdi) - serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previo usly applied to the tms input. the registers are described in a subsequent section. the received input da ta is sampled at the rising edge of the tck pulse. this pin is internally pulled to high when it is not driven from an external source. ? test data output (tdo) - depending on the sequence previously applied to the tms input, the contents of either the instruction register or test data register ar e serially shifted out towards tdo. the data from tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) - resets the jtag scan structure. this pin is internally pulled to high when it is not driven from an external source. 11.2 instruction register the ZL50017 uses the public instructions defined in t he ieee-1149.1 standard. the jtag interface contains a four-bit instruction register. instructions are serially loaded into the in struction register from the tdi when the tap controller is in its shifted-or state. these instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data bet ween tdi and tdo during data register scanning. 11.3 test data registers as specified in the ieee-1149.1 standard, the ZL50017 jt ag interface contains three test data registers: ? the boundary-scan register - the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the zl 50017 core logic. ? the bypass register - the bypass register is a single stage shift r egister that provides a one-bit path from tdi to tdo. ? the device identification register - the jtag device id for the ZL50017 is 0c36114b h 11.4 bsdl a boundary scan description language (bsdl) file is availabl e from zarlink semiconductor to aid in the use of the ieee-1149.1 test interface. version <31:28> 0000 part number <27:12> 1100 0011 0110 0001 manufacturer id <11:1> 0001 0100 101 lsb <0> 1 ZL50017 data sheet 26 zarlink semiconductor inc. 12.0 register address mapping address a13 - a0 cpu access register name abbreviation reset by 0000 h r/w control register cr switch/hardware 0001 h r/w internal mode selection register ims switch/hardware 0002 h r/w software reset register srr hardware only 0008 h r/w data rate selection register drsr switch/hardware 0100 h - 010f h r/w stream input control registers 0 - 15 sicr0 - 31 switch/hardware 0200 h - 020f h r/w stream output control register s 0 - 15 socr0 - 15 switch/hardware table 4 - address map for registers (a13 = 0) ZL50017 data sheet 27 zarlink semiconductor inc. 13.0 detailed register description bit name description 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9fpinpos input frame pulse (fpi) position when this bit is low, fpi straddles frame boundary (as defined by st-bus). when this bit is high, fpi starts from frame boundary (as defined by gci-bus) 8ckinp clock input (cki) polarity when this bit is low, the cki falling edge aligns with the frame boundary. when this bit is high, the cki risi ng edge aligns with the frame boundary. 7fpinp frame pulse input (fpi) polarity when this bit is low, the input frame puls e fpi has the negative frame pulse format. when this bit is high, the input frame pulse fpi has the positive frame pulse format. 6 - 5 ckin1 - 0 input clock (cki) and fram e pulse (fpi) selection 4 varen variable delay mode enable when this bit is low, the variable delay mode is disabled on a device-wide basis. when this bit is high, the variable delay mode is enabled on a device-wide basis. 3 mbpe memory block programming enable when this bit is high, the connection me mory block programming mode is enabled to program the connection memory. when it is low, the memory block programming mode is disabled. table 5 - control register (cr) bits external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 000fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 ckin1 - 0 fpi active period cki 00 61 ns 16.384 mhz 01 122 ns 8.192 mhz 10 244 ns 4.096 mhz 11 reserved ZL50017 data sheet 28 zarlink semiconductor inc. 2osb output stand by bit: this bit enables the stio0 - 1 serial outputs. the following table describes the hiz control of the serial data outputs: note: unused output streams are tristated (s tio = hiz). refer to socr0 - 15 (bit 2 - 0). 1 - 0 ms1 - 0 memory select bits these two bits are used to select connection memory low, connection high or data mem- ory for access by cpu: bit name description table 5 - control register (cr) bits (continued) external read/write address: 0000 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 000fpin pos ckinp fpinp ckin 1 ckin 0 var en mbpe osb ms1 ms0 reset pin srstsw (in srr) ode pin osb bit stio0 - 15 0xxx hiz 11xx hiz 100x hiz 1010 hiz 1011 active (controlled by cm) ms1 - 0 memory selection 00 connection memory low read/write 01 reserved 10 data memory read 11 reserved ZL50017 data sheet 29 zarlink semiconductor inc. bit name description 15 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8stio_pd_ en stio pull-down enable when this bit is low, the pull-down re sistors on all stio pads will be disabled. when this bit is high, t he pull-down resistors on all stio pads will be enabled. 7unused reserved. in normal functional mode, these bits must be set to zero. 6bd bi-directional control 5 - 4 unused reserved. in normal functional mode, these bits must be set to zero. 3 - 1 bpd2 - 0 block programming data these bits refer to the value to be loaded into the connection memory, whenever the memory block programming feature is acti vated. after the mbpe bit in the control register is set to high and the mbps bit in th is register is set to high, the contents of the bits bpd2 - 0 are loaded into bits 2 - 0 of the connection memory low. bits 15 - 3 of the connection memory low. 0 mbps memory block programming start: a zero to one transition of this bit starts the memory block progr amming function. the mbps and bpd2 - 0 bits in this register must be defined in the same write operation. once the mbpe bit in the control register is set to high, the device requires two frames to complete the block programmin g. after the programmi ng function has fin- ished, the mbps bit returns to low, indicating the operation is completed. when mbps is high, mbps or mbpe can be set to low to abort the pr ogramming operation. whenever the microprocessor writes a one to the mbps bit, the block programming function is started. as long as this bit is hi gh, the user must maintain the same logical value to the other bits in this register to avoid any change in the device setting. table 6 - internal mode selection register (ims) bits external read/write address: 0001 h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000000stio_ pd_en 0 bd 0 0 bpd 2 bpd 1 bpd 0 mbps bdl stio0 - 15 operation 0 normal operation: sti0-15 are inputs stio0-15 are outputs 1 bi-directional operation: sti0-15 tied low internally stio0-15 are bi-directional ZL50017 data sheet 30 zarlink semiconductor inc. bit name description 15 - 2 unused reserved in normal functional mode, these bits must be set to zero. 1srstsw software reset bit for switch when this bit is low, switching blocks are in normal operation. when this bit is high, switching blocks are in software reset state. refer to table 12, ?address map for registers (a13 = 0)? on page 32 for details regarding which registers are affected. 0unused reserved in normal functional mode, these bits must be set to zero. table 7 - software reset register (srr) bits bit name description 15 - 4 unused reserved in normal functional mode, these bits must be set to zero. 3 - 0 dr3 - 0 input/output data rate selection bits: these bits set the data rate for both input and output streams table 8 - data rate selection register external read/write address: 0002 h reset value: 0000 h 15141312111098765432 1 0 00000000000000srst sw 0 external read/write address: 0008 h reset value: 0000 h 15141312111098765432 1 0 000000000000dr3dr2dr1dr0 dr3 - 0 stio0 - 15 operation 0000 reserved 0001 2.048 mbps 0010 4.096 mbps 0011 8.192 mbps 0100 16.384 mbps 0101 - 1111 reserved ZL50017 data sheet 31 zarlink semiconductor inc. bit name description 15 - 1 unused reserved in normal functional mode, these bits are zero. 0 perr program error (read only) this bit is set high when the total number of input/output channels is programmed to be more than the maximum capacity of 102 4, in which case the input/output channels beyond the maximum capacity should be di sabled.this bit will be cleared automati- cally after the total number of active str eams/channels is correctly programmed to be 1024 channels or below. table 9 - internal flag register (ifr) bits - read only bit name description 15 - 9 unused reserved in normal functional mode, these bits must be set to zero . 8 - 6 stin[n]bd2 - 0 input stream[n] bit delay bits. the binary value of these bits refers to the number of bits that the input stream will be delayed relative to fpi. the maxi mum value is 7. zero means no delay. 5 - 4 stin[n]smp1 - 0 input data sampling point selection bits 3 - 1 unused reserved in normal functional mode, these bits must be set to zero . table 10 - stream input control register 0 - 15 (sicr0 - 15) bits external read address: 0010 h reset value: 0000 h 15141312111098765432 1 0 00000000000000 0 perr external read/write address: 0100 h - 010f h reset value: 0000 h 1514131211109876543210 0000000stin[n] bd2 stin[n] bd1 stin[n] bd0 stin[n] smp1 stin[n] smp0 000stin[n] en stin[n]smp1-0 sampling point (2.048 mbps, 4.096 mbps, 8.192 mbps streams) sampling point 16.384 mbps streams) 00 3/4 point 1/2 point 01 1/4 point 10 2/4 point 4/4 point 11 4/4 point ZL50017 data sheet 32 zarlink semiconductor inc. 0stin[n]en input stream enable bit when this bit is high the input stream is enabled. when this bit is low the input stream is ignored note: [n] denotes input stream from 0 - 15 . bit name description 15 - 9 unused reserved in normal functional mode, these bits must be set to zero. 8 - 7 sto[n]fa1 - 0 output stream[n] fract ional advancement bits 6 - 4 sto[n]ad2 - 0 output stream[n] bit ad vancement selection bits the binary value of these bits refers to the number of bits that the output stream is to be advanced relative to fpi. the maximum value is 7. zero means no advancement. 3 - 1 unused reserved in normal functional mode, these bits must be set to zero . 0 sto[n]en output stream enable bit when this bit is high the output stre am is enabled. when this bit is low the output stream is set to high impedance note: [n] denotes output stream from 0 - 15 . table 11 - stream output control register 0 - 15 (socr0 - 15) bits bit name description table 10 - stream input control register 0 - 15 (sicr0 - 15) bits (continued) external read/write address: 0100 h - 010f h reset value: 0000 h 1514131211109876543210 0000000stin[n] bd2 stin[n] bd1 stin[n] bd0 stin[n] smp1 stin[n] smp0 000stin[n] en external read/write address: 0200 h - 020f h reset value: 0000 h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0000 0 0 0 sto[n] fa1 sto[n] fa0 sto[n] ad2 sto[n] ad1 sto[n] ad0 0 0 0 sto[n] en sto[n]fa1-0 advancement (2.048 mbps, 4.096 mbps, 8.192 mbps streams) advancement (16.384 mbps streams) 00 0 0 01 1/4 bit 2/4 10 2/4 bit reserved 11 3/4 bit ZL50017 data sheet 33 zarlink semiconductor inc. 14.0 memory 14.1 memory address mappings when a13 is high, the data or connection memory can be accessed by the microprocessor port. bit 1 - 0 in the control register determine the access to th e data or connection memory (cm_l or cm_h). msb (note 1) stream address (st0 - 31) channel address (ch0 - 127) a13 a12a11a10 a9 a8 stream [n] a7a6a5a4a3a2a1a0 channel [n] 1 1 1 1 1 1 1 1 1 . . . . . 1 1 0 0 0 0 0 0 0 0 0 . . . . . 0 0 0 0 0 0 0 0 0 0 1 . . . . . 1 1 0 0 0 0 1 1 1 1 0 . . . . . 1 1 0 0 1 1 0 0 1 1 0 . . . . . 1 1 0 1 0 1 0 1 0 1 0 . . . . . 0 1 stream 0 stream 1 stream 2 stream 3 stream 4 stream 5 stream 6 stream 7 stream 8 . . . . . stream 14 stream 15 0 0 . . 0 0 0 0 . . 0 0 . . 0 0 . . . . 1 1 0 0 . . 0 0 0 0 . . 0 0 . . 1 1 . . . . 1 1 0 0 . . 0 0 1 1 . . 1 1 . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . . 1 1 . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 . 1 1 . . 1 1 . . . . 1 1 0 0 . . 1 1 0 0 1 1 . . 1 1 . . . . 1 1 0 1 . . 0 1 0 1 . . 0 1 . . 0 1 . . . . 0 1 ch 0 ch 1 . . ch 30 ch 31 (note 2) ch 32 ch 33 . . ch 62 ch 63 (note 3) . . ch126 ch 127 (note 4) . . . . ch 254 ch 255 (note 5) notes: 1. a13 must be high for access to data and connection memory positions. a13 must be low to access internal registers. 2. channels 0 to 31 are used when serial stream is at 2.048 mbps. 3. channels 0 to 63 are used when serial stream is at 4.096 mbps. 4. channels 0 to 127 are used when serial stream is at 8.192 mbps. 5. channels 0 to 255 are used when serial stream is at 16.384 mbps. table 12 - address map for memory locations (a13 = 1) ZL50017 data sheet 34 zarlink semiconductor inc. 14.2 connection memory low (cm_l) bit assignment when the cmm bit (bit 0) in the connection memory low is zero, the per-channel transmission is set to the normal channel-switching. the connection memory low bit assi gnment for the channel transmission mode is shown in table 13 on page 34. bit name description 15 unused reserved in normal functional mode, these bits must be set to zero. 14 v/c variable/constant delay control when this bit is low, the output data for this channel will be taken from con- stant delay memory. when this bit is set to high, the output data for this channel will be taken from variable delay memory. note that varen must be set in control register first. 13 unused reserved. in normal functional mode, this bit must be set to zero. 12 - 9 ssa3 - 0 source stream address the binary value of these 4 bits re presents the input stream number. 8 - 1 sca7 - 0 source channel address the binary value of these 8 bits re presents the input channel number. 0 cmm = 0 connection memory mode = 0 if this is low, the connection memory is in the normal switching mode. bit 13 - 1 are the source stream number and channel number. table 13 - connection memory low (cm_l) bit assignment when cmm = 0 151413121110987654321 0 0v/c 0 ssa 3 ssa 2 ssa 1 ssa 0 sca 7 sca 6 sca 5 sca 4 sca 3 sca 2 sca 1 sca 0 cmm =0 ZL50017 data sheet 35 zarlink semiconductor inc. when cmm is one, the device is programmed to perform one of the special per-channel transmission modes. bits pcc0 and pcc1 from connection memory are used to select the per-channel tristate or message mode as shown in table 14 on page 35. bit name description 15 - 11 unused reserved in normal functional mode, these bits must be set to zero. 10 - 3 msg7 - 0 message data bits 8-bit data for the message mode. not used in the per-channel tristate. 2 - 1 pcc1 - 0 per-channel control bits these two bits control the correspondi ng entry?s value on the stio stream . 0 cmm = 1 connection memory mode = 1 if this is high, the connection memory is in the per-channel control mode which is per-channel tristate or per-channel message mode. table 14 - connection memory low (cm_l) bit assignment when cmm = 1 151413121110987654321 0 0 0000msg 7 msg 6 msg 5 msg 4 msg 3 msg 2 msg 1 msg 0 pcc 1 pcc 0 cmm =1 pc c1 pc c0 channel output mode 0 0 per channel tristate 0 1 message mode 10 reserved 11 reserved ZL50017 data sheet 36 zarlink semiconductor inc. 15.0 dc parameters * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. * note 1: maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage ( v in ). absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage v dd_io -0.5 5.0 v 2 core supply voltage v dd_core -0.5 2.5 v 3 input voltage v i_3v -0.5 v dd + 0.5 v 4 input voltage (5 v-tolerant inputs) v i_5v -0.5 7.0 v 5 continuous current at digital outputs i o 15 ma 6 package power dissipation p d 1.5 w 7 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated . characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 25 +85 c 2 positive supply v dd_io 3.0 3.3 3.6 v 3 positive supply v dd_core 1.71 1.8 1.89 v 4 input voltage v i 03.3v dd_io v 5 input voltage on 5 v-tolerant inputs v i_5v 05.05.5v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 supply current - v dd_core i dd_core 75 ma 2 supply current - v dd_io i dd_io 40 ma c l =30pf 3 input high voltage v ih 2.0 v 4 input low voltage v il 0.8 v 5 input leakage (input pins) input leakage (bi-di rectional pins) i il i bl 5 5 a a 0 ZL50017 data sheet 38 zarlink semiconductor inc. figure 15 - motorola non-multiplexed bus timing - read access ac electrical characteristics - motorola non-multiplexed bus mode - read access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2ds de-asserted time t dsd 15 ns 3cs setup to ds falling t css 0ns 4r/w setup to ds falling t rws 10 ns 5 address setup to ds falling t as 5ns 6cs hold after ds rising t csh 0ns 7r/w hold after ds rising t rwh 0ns 8 address hold after ds rising t ah 0ns 9 data setup to dta low t ds 8nsc l = 50 pf 10 data active to high impedance t dhz 8nsc l = 50 pf, r l = 1 k (note 1) 11 acknowledgement delay time. from ds low to dta low: registers memory t akd 75 185 ns ns c l = 50 pf c l = 50 pf 12 acknowledgement hold time. from ds high to dta high t akh 412nsc l = 50 pf, r l = 1 k (note 1) 13 dta drive high to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 10.2 on page 24) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 d0-d15 t csh t ah t rws r/w t as t rwh t akd t ds t akh dta v ct v ct v ct v ct v ct v ct valid address valid read data t css t dsd cs t akz t csd t dhz ZL50017 data sheet 39 zarlink semiconductor inc. figure 16 - motorola non-multiplexed bus timing - write access ac electrical characteristics - motorola non-multiplexed bus mode - write access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2ds de-asserted time t dsd 15 ns 3cs setup to ds falling t css 0ns 4r/w setup to ds falling t rws 10 ns 5 address setup to ds falling t as 5ns 6 data setup to ds falling t ds 0nsc l = 50 pf 7cs hold after ds rising t csh 0ns 8r/w hold after ds rising t rwh 0ns 9 address hold after ds rising t ah 0ns 10 data hold from ds rising t dh 5nsc l = 50 pf, r l = 1 k (note 1) 11 acknowledgement delay time. from ds low to dta low: registers memory t akd 55 150 ns ns c l = 50 pf c l = 50 pf 12 acknowledgement hold time. from ds high to dta high t akh 412nsc l = 50 pf, r l = 1 k (note 1) 13 dta drive high to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 10.2 on page 24) must be applied before the first microprocessor access is performed after the reset pin is set high. ds a0-a13 t csh t ah t rws r/w t as t rwh t akd t akh dta v ct v ct v ct v ct v ct t css t dsd cs t akz d0-d15 t dh t ds v ct valid write data t csd valid address ZL50017 data sheet 40 zarlink semiconductor inc. figure 17 - intel non-multiplexed bus timing - read access ac electrical characteristics - intel non-multiplexed bus mode - read access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2rd setup to cs falling t rs 10 ns 3wr setup to cs falling t ws 10 ns 4 address setup to cs falling t as 5ns 5rd hold after cs rising t rh 0ns 6wr hold after cs rising t wh 0ns 7 address hold after cs rising t ah 0ns 8 data setup to rdy high t ds 8nsc l = 50 pf 9 data active to high impedance t csz 7nsc l = 50 pf, r l = 1 k (note 1) 10 acknowledgement delay time. from cs low to rdy high: registers memory t akd 175 185 ns ns c l = 50 pf c l = 50 pf 11 acknowledgement hold time. from cs high to rdy low t akh 412nsc l = 50 pf, r l = 1 k (note 1) 12 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (see section 10.2 on page 24) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t ws wr t wh t akd t ds t akh rdy v ct v ct v ct v ct v ct valid address valid read data t csd t akz t rs rd t rh v ct t as t csz ZL50017 data sheet 41 zarlink semiconductor inc. figure 18 - intel non-multiple xed bus timing - write access ac electrical characteristics - intel non-multiplexed bus mode - write access characteristics sym. min. typ. ? max. units test conditions 2 1cs de-asserted time t csd 15 ns 2wr setup to cs falling t ws 10 ns 3rd setup to cs falling t rs 10 ns 4 address setup to cs falling t as 5ns 5 data setup to cs falling t ds 0nsc l = 50 pf 6wr hold after cs rising t wh 0ns 7rd hold after cs rising t rh 0ns 8 address hold after cs rising t ah 10 ns 9 data hold after cs rising t dh 5nsc l = 50 pf, r l = 1 k (note 1) 10 acknowledgement delay time. from cs low to rdy high: registers memory t akd 55 150 ns ns c l = 50 pf c l = 50 pf 11 acknowledgement hold time. from cs high to rdy low t akh 412nsc l = 50 pf, r l = 1 k (note 1) 12 rdy drive low to hiz t akz 8ns note 1: high impedance is measured by pulling to th e appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . note 2: a delay of 500 s to 2 ms (section 10.2 on page 24) must be applied before the first microprocessor access is performed after the reset pin is set high. cs a0-a13 d0-d15 t ah t rs rd t rh t akd t akh rdy v ct v ct v ct v ct v ct valid address t csd t akz t ws wr t wh v ct t as valid write data t ds t dh ZL50017 data sheet 42 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 19 - jtag test port timing diagram ac electrical characteristics ? - jtag test port timing characteristic sym. min. typ. ? max. units notes 1 tck clock period t tckp 100 ns 2 tck clock pulse width high t tckh 20 ns 3 tck clock pulse width low t tckl 20 ns 4 tms set-up time t tmss 10 ns 5 tms hold time t tmsh 10 ns 6 tdi input set-up time t tdis 20 ns 7 tdi input hold time t tdih 60 ns 8 tdo output delay t tdod 30 ns c l = 30 pf 9trst pulse width t trstw 200 ns t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst ZL50017 data sheet 43 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 00 (16.384 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 40 61 115 ns 2 fpi input frame pulse setup time t fpis 20 ns 3 fpi input frame pulse hold time t fpih 20 ns 4 cki input clock period t ckip 55 61 67 ns 5 cki input clock high time t ckih 27 34 ns 6 cki input clock low time t ckil 27 34 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ac electrical characteristics ? - fpi and cki timing when ckin1-0 bits = 01 (8.192 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 122 220 ns 2 fpi input frame pulse setup time t fpis 45 ns 3 fpi input frame pulse hold time t fpih 45 ns 4 cki input clock period t ckip 110 122 135 ns 5 cki input clock high time t ckih 55 69 ns 6 cki input clock low time t ckil 55 69 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns ZL50017 data sheet 44 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. figure 20 - frame pulse input and clock input timing diagram (st-bus) figure 21 - frame pulse input and clock input timing diagram (gci-bus) ac electrical character istics - fpi and cki timing when ckin1-0 bits = 10 (4.096 mhz) characteristic sym. min. typ. ? max. units notes 1 fpi input frame pulse width t fpiw 90 244 420 ns 2 fpi input frame pulse setup time t fpis 110 ns 3 fpi input frame pulse hold time t fpih 110 ns 4 cki input clock period t ckip 220 244 270 ns 5 cki input clock high time t ckih 110 135 ns 6 cki input clock low time t ckil 110 135 ns 7 cki input clock rise/fall time t r cki, t f cki 3 ns 8 cki input clock cycle to cycle variation t cvc 020ns t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki t fpiw fpi t fpih t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki ZL50017 data sheet 45 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25c, vdd_core at 1.8 v and vdd_io at 3.3 v and are for design aid only: not guaranteed and not subject to produc- tion testing. note 1: high impedance is measured by pulling to th e appropriat e rail with r l , with timing corrected to cancel the time taken to discharge c l . ac electrical characteristics ? - st-bus/gci-bus input timing characteristic sym. min. typ. ? max. units test conditions 1 sti setup time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sis2 t sis4 t sis8 t sis16 5 5 5 5 ns ns ns ns 2sti hold time 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t sih2 t sih4 t sih8 t sih16 8 8 8 8 ns ns ns ns 3 stio delay - active to active @2.048 mbps @4.096 mbps @8.192 mbps @16.384 mbps t sod2 t sod4 t sod8 t sod16 -6 -6 -6 -6 0 0 0 0 ns ns ns ns c l = 30 pf 4 stio delay - active to high-z stio delay - high-z to active 2.048 mbps 4.096 mbps 8.192 mbps 16.384 mbps t dz t zd -8 -8 -8 -8 0 0 0 0 ns ns ns ns r l = 1 k, c l = 30 pf, see note 1. 5 output drive enable (ode) delay - high-z to active t zd_od e 260 ns 6 output drive enable (ode) delay - active to high-z t dz_od e 260 ns ZL50017 data sheet 46 zarlink semiconductor inc. figure 22 - st-bus input and output timing di agram when operated at 2, 4, 8 and 16 mbps v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit7 ch0 bit6 ch0 t sis4 t sih4 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit0 ch63 bit7 ch0 bit6 ch0 bit5 ch0 bit4 ch0 bit3 ch0 bit2 ch0 bit1 ch0 bit0 ch0 bit1 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 15 sti0 - 15 sti0 - 15 v ct v ct bit0 ch31 v ct input frame boundary bit0 ch127 8.192 mbps 4.096 mbps 2.048 mbps stio0 - 31 stio0 - 31 stio0 - 31 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit7 ch31 t sod2 /t dz /t zd t sod4 /t dz /t zd t sod8 /t dz /t zd v ct v ct v ct bit7 ch127 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch127 bit7 ch255 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch255 bit6 ch255 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch1 bit1 ch1 bit2 ch1 bit3 ch1 bit4 ch1 bit5 ch1 v ct t sod16 /t dz /t zd 16.384 mbps stio0 - 31 ZL50017 data sheet 47 zarlink semiconductor inc. figure 23 - gci-bus input and output timing di agram when operated at 2, 4, 8 and 16 mbps v tt cki fpi (16.384 mhz) cki fpi (8.192 mhz) cki fpi (4.096 mhz) t sis2 t sih2 bit0 ch0 bit1 ch0 t sis4 t sih4 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch127 8.192 mbps 4.096 mbps 2.048 mbps t sis8 t sih8 sti0 - 15 sti0 - 15 sti0 - 15 v ct v ct bit7 ch31 v ct input frame boundary bit7 ch127 8.192 mbps 4.096 mbps 2.048 mbps stio0 - 31 stio0 - 31 stio0 - 31 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit7 ch63 bit0 ch0 bit1 ch0 bit7 ch31 t sod2 t sod4 t sod8 v ct v ct v ct bit7 ch127 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch0 bit6 ch0 bit7 ch0 bit6 ch127 bit7 ch255 bit0 ch0 bit1 ch0 bit2 ch0 bit3 ch0 bit4 ch0 bit5 ch255 bit6 ch255 bit5 ch0 bit6 ch0 bit7 ch0 bit0 ch1 bit1 ch1 bit2 ch1 bit3 ch1 bit4 ch1 bit5 ch1 v ct t sod16 16.384 mbps stio0 - 31 c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes b 214440 1 26june03 c zarlink semiconductor 2003 all rights reserved. apprd. issue date acn package code previous package codes www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - 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